Switching regulator and lsi system

ABSTRACT

In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors  21  through  23  having different on-resistances, which are operated in a descending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor  102.

TECHNICAL FIELD

[0001] The present invention relates to a technique concerning aswitching regulator, and more particularly, it relates to a technique toreduce switching noise.

BACKGROUND ART

[0002] Recently, portable electronic equipment such as a portabletelephone and a notebook personal computer has been remarkably spread.With the spread of such equipment, a technique to reduce powerconsumption has become indispensable in the field of semiconductortechnology. In order to suppress the power consumption of an LSI, it iseffective to reduce the power-supply voltage of the LSI itself, and forthis purpose, a highly efficient power-supply voltage converting circuitis necessary.

[0003] A switching regulator is known to have much higher efficiencythan a linear regulator due to its operation principle, and varioussystems for a switching regulator have been studied and developed. Inaccordance with increase of the operation speed and decrease of thepower consumption of an LSI, there are increasing demands for aswitching regulator with higher efficiency and higher switching speed.

[0004]FIG. 18 is a diagram for showing a basic circuit configuration ofa conventional switching regulator, that is, a synchronous rectifiablebuck switched-mode power-supply (DC/DC converter). A DC power-supply 1is a source for generating the output of this switching regulator, andis a target to be chopped. The DC power-supply 1 is connected, at itspower-supply port, to the source terminal of an output switchingtransistor 2 constructed from a P-type MOS transistor, and is connected,at its GND port, to the source terminal of a rectifier switchingtransistor 3 constructed from an N-type MOS transistor.

[0005]FIG. 19 is a timing chart for showing the operation of theswitching regulator of FIG. 18. A controller 5 compares an outputvoltage Vout with a reference voltage Vref, and controls on/offoperations of the switching transistors 2 and 3 on the basis of theresult of the comparison. A voltage comparator 4 compares the outputvoltage Vout with the reference voltage Vref, and a pulse generatingcircuit 6 outputs a pulse signal SC for controlling the on/offoperations on the basis of the result of the comparison. The signal SCis supplied to gate driving buffers 8 and 9 of the switching transistors2 and 3. The drain voltage VD of each of the switching transistors 2 and3 is chopped by the on/off operation of the switching transistor 2 or 3and a diode 11, and the chopped voltage is smoothed by a smoothingcircuit 14 including an inductance device 12 and a capacitor 13, so asto be output as the output voltage Vout. The conversion efficiency isdefined as follows:

[0006] Conversion efficiency=(Output power)/(Input power)

Problems to be Solved by the Invention

[0007] In order to keep high conversion efficiency in the conventionalswitching regulator, it is necessary to optimize a switching size bydecreasing the on-resistances of the switching transistors 2 and 3 asmuch as possible, or/and to decrease an AC loss by increasing aswitching frequency so as to conduct rapid switching. There arises,however, a problem that the rapid switching causes large switchingnoise.

[0008] Specifically, there exists a so-called parasitic inductor 102 ona power-supply line as is shown in FIG. 18. When the source-drainvoltage VDS of the switching transistors 2 and 3 is large, abruptcurrent change caused by the switching operation leads to occurrence ofdi/dt noise derived from the parasitic inductor 102. This noisefluctuates the power-supply voltage level in every switching operation,resulting in causing similar noise also in the output voltage Vout. As aresult, L·di/dt switching noise derived from the parasitic inductor 102of the power-supply line is unavoidably caused in the out put voltageVout.

[0009] In order to reduce such switching noise, for example, a capacityinserting resonant switching regulator is conventionally used. Theresonant switching regulator conducts ZVC (zero voltage switching) byutilizing LC resonance. The resonant switching regulator, however, has aproblem of a very complicated configuration of its control circuit andis difficult to timely control. Furthermore, this resonant switchingregulator has another problem that as the output current is larger, theAC loss is larger, resulting in decreasing the conversion efficiency.

Disclosure of the Invention

[0010] An object of the invention is reducing switching noise of aswitching regulator while keeping high conversion efficiency.

[0011] Specifically, the switching regulator of this invention comprisesplural output switching transistors operated in a predetermined order inat least one of an on operation and an off operation thereof.

[0012] According to the invention, the plural output switchingtransistors are operated in the predetermined order in at least one ofthe on operation and the off operation thereof. As a result, abruptcurrent change can be suppressed in the switching operation.Accordingly, di/dt noise derived from a parasitic inductor can bereduced.

[0013] In the switching regulator, the plural output switchingtransistors are preferably turned on in a descending order ofon-resistance in the on operation thereof, and the plural outputswitching transistors are preferably turned off in an ascending order ofon-resistance in the off operation thereof.

[0014] In the switching regulator, the plural output switchingtransistors are preferably turned on in an ascending order of transistorwidth in the on operation thereof, and the plural output switchingtransistors are preferably turned off in a descending order oftransistor width in the off operation thereof.

[0015] In the switching regulator, one of the plural output switchingtransistors that is turned on first preferably has a drain current valuein a non-saturation region larger than a maximum load current value ofthe switching regulator.

[0016] Preferably, in the switching regulator, the plural outputswitching transistors are divided into plural groups, and in the onoperation thereof, the plural output switching transistors are turned onby group in an ascending order of the number of output switchingtransistors belonging to each group, and in the off operation thereof,the plural output switching transistors are turned off by group in adescending order of the number of output switching transistors belongingto each group.

[0017] The switching regulator preferably further comprises pluraldriving circuits provided correspondingly to the plural output switchingtransistors each for operating a corresponding one of the outputswitching transistors in accordance with a driving signal thereof, andat least one of the plural driving circuits preferably includes aninverter for driving a gate of the corresponding one of the outputswitching transistors in accordance with the driving signal; and aconstant current source circuit for controlling a current flowingthrough the inverter to be constant.

[0018] The at least one of the plural driving circuits preferablyincludes a current controlling circuit for controlling, in accordancewith a load current quantity of the switching regulator, an amplitude ofthe current flowing through the inverter controlled by the constantcurrent source circuit. Also, the at least one of the plural drivingcircuits preferably includes a non-overlap circuit that receives thedriving signal and supplies a signal to the inverter for preventing aP-type MOS transistor and an N-type MOS transistor included in theinverter from being in an on state at the same time.

[0019] In the switching regulator, one of the plural output switchingtransistors having a comparatively large size is preferably placedcomparatively closer to I/O pads of an LSI including the switchingregulator and another of the plural output switching transistors havinga comparatively small size is preferably placed comparatively fartherfrom the I/O pads of the LSI.

[0020] Furthermore, the switching regulator preferably further comprisesa timing setting circuit provided correspondingly to at least one of theplural output switching transistors, the timing setting circuit settingtiming of turning on or off the corresponding one of the outputswitching transistors in accordance with a load current value of theswitching regulator.

[0021] Moreover, the switching regulator preferably further comprisesplural rectifier switching transistors operated in a predetermined orderin at least one of an on operation and an off operation thereof.Additionally, the plural rectifier switching transistors are preferablyturned on in a descending order of on-resistance in the on operationthereof, and the plural rectifier switching transistors are preferablyturned off in an ascending order of on-resistance in the off operationthereof.

[0022] Furthermore, the switching regulator preferably further comprisesplural driving circuits provided correspondingly to the plural rectifierswitching transistors each for operating a corresponding one of theplural rectifier switching transistors in accordance with a drivingsignal thereof, and at least one of the plural driving circuitspreferably includes an inverter for driving a gate of the correspondingone of the rectifier switching transistors in accordance with thedriving signal; and a constant current source circuit for controlling acurrent flowing through the inverter to be constant.

[0023] Moreover, the switching regulator preferably further comprises atiming setting circuit provided correspondingly to at least one of theplural rectifier switching transistors for setting timing of turning onor off the corresponding one of the output switching transistors inaccordance with a load current value of the switching regulator.

[0024] Also, the switching regulator preferably further comprises alogic circuit for preventing the plural rectifier switching transistorsfrom turning on when at least one of the plural output switchingtransistors is in an on state.

[0025] Also, the switching regulator preferably further comprises acontroller for controlling the on operation and the off operation of theplural output switching transistors, and in the on operation of theplural output switching transistors, the controller turns on one of theoutput switching transistors that is to be turned on first, and the restof the output switching transistors are successively turned on inaccordance with change of a gate signal of any of the output switchingtransistors that is turned on immediately before, and in the offoperation of the plural output switching transistors, the controllerturns off one of the output switching transistors that is to be turnedoff first, and the rest of the output switching transistors aresuccessively turned off in accordance with change of a gate signal ofany of the output switching transistors that is turned off immediatelybefore.

[0026] In addition, the switching regulator preferably further comprisesplural rectifier switching transistors operated in a predetermined orderin an on operation and an off operation thereof, and in the on operationof the plural output switching transistors, the controller turns off oneof the rectifier switching transistors that is to be turned off first,and the rest of the rectifier switching transistors are successivelyturned off in accordance with change of a gate signal of any of therectifier switching transistors that is turned off immediately before,and one of the output switching transistors that is to be turned onfirst is turned on in accordance with change of a gate signal of any ofthe rectifier switching transistors that is turned off lastly, and therest of the output switching transistors are successively turned on inaccordance with change of a gate signal of any of the output switchingtransistors that is turned on immediately before; and in the offoperation of the plural output switching transistors, the controllerturns off one of the output switching transistors that is to be turnedoff first, and the rest of the output switching transistors aresuccessively turned off in accordance with change of a gate signal ofany of the output switching transistors that is turned off immediatelybefore, and one of the rectifier switching transistors that is to beturned on first is turned on in accordance with change of a gate signalof any of the output switching transistors that is turned off lastly,and the rest of the rectifier switching transistors are successivelyturned on in accordance with change of a gate signal of any of therectifier switching transistors that is turned on immediately before.

[0027] Alternatively, the LSI system of this invention comprises theswitching regulator of this invention; and an LSI core part operated bya voltage supplied from the switching regulator.

Brief Description of Drawings

[0028]FIG. 1 is a diagram for showing the configuration of a switchingregulator according to Embodiment 1 of the invention;

[0029]FIG. 2 is a diagram for showing the internal configuration of apulse generating circuit 16 of FIG. 1;

[0030]FIG. 3 is a diagram for showing change with time of signals SG,SA1 through SA3 and SB1 through SB3 in the configuration of FIG. 1;

[0031]FIG. 4 is a diagram for showing the characteristics of outputswitching transistors 21 through 23 of FIG. 1;

[0032]FIG. 5 is a diagram for showing another configuration of pluraloutput transistors;

[0033]FIG. 6 is a diagram for showing the characteristics of transistorsbelonging to respective groups 24 through 26;

[0034]FIG. 7 is a circuit diagram for showing an internal configurationof a driving circuit 40 of FIG. 1;

[0035]FIG. 8 is a circuit diagram for showing another internalconfiguration of the driving circuit 40 of FIG. 1;

[0036]FIG. 9 is a circuit diagram for showing still another internalconfiguration of the driving circuit 40 of FIG. 1;

[0037]FIG. 10 is a diagram for showing an exemplified layout of theoutput switching transistors 21 through 23 and rectifier switchingtransistors 31 through 33 of FIG. 1;

[0038]FIG. 11 is a diagram for showing the configuration of a switchingregulator according to Embodiment 2 of the invention;

[0039]FIG. 12(a) is a diagram for showing the internal configuration ofan edge detecting circuit 60 of FIG. 11 and FIG. 12(b) is a timing chartof input/output of the edge detecting circuit 60 of FIG. 12(a);

[0040]FIG. 13 is a diagram for showing the configuration of a switchingregulator according to Embodiment 3 of the invention;

[0041]FIG. 14 is a diagram for showing part of the configuration of aswitching regulator according to Embodiment 4 of the invention;

[0042]FIG. 15 is a diagram for showing modification of part of theconfiguration of FIG. 14;

[0043]FIG. 16 is a diagram for showing the configuration of a switchingregulator according to Embodiment 5 of the invention;

[0044]FIG. 17 is a diagram for showing the configuration of an LSIsystem equipped with a switching regulator of this invention;

[0045]FIG. 18 is a diagram for showing the configuration of aconventional switching regulator; and

[0046]FIG. 19 is a voltage waveform diagram of the conventionalswitching regulator.

Best Mode for Carrying Out the Invention

[0047] (EMBODIMENT 1)

[0048]FIG. 1 is a diagram for showing the configuration of a switchingregulator of Embodiment 1 of the invention. The switching regulator ofFIG. 1 is a synchronous rectifiable buck switched-mode regulator (DC/DCconverter).

[0049] A DC power-supply 1 is a source for generating the output of theswitching regulator. The DC power-supply 1 is connected, at itspower-supply port, to the source terminals of plural output switchingtransistors 21, 22 and 23 each constructed from a P-type MOS transistor,and is connected, at its GND port, to the source terminals of pluralrectifier switching transistors 31, 32 and 33 each constructed from anN-type MOS transistor. The drain terminals of the output switchingtransistors 21, 22 and 23 and the rectifier switching transistors 31, 32and 33 are connected to a diode 11 and a smoothing circuit 10 includingan inductance device 12 and a capacitor 13.

[0050] A controller 15 controls the on/off operations of the switchingtransistors 21 through 23 and 31 through 33 in accordance with an outputvoltage Vout of the switching regulator output from the smoothingcircuit 10. In the controller 15, a voltage comparator 4 compares theoutput voltage Vout with a reference voltage Vref and outputs a signalSG corresponding to the result of the comparison. In response to thesignal SG, a pulse generating circuit 16 outputs signals SA1 through SA3and SB1 through SB3 for respectively controlling the on/off operationsof the switching transistors 21 through 23 and 31 through 33.

[0051] A driving circuit 40 is provided to each of the switchingtransistors 21 through 23 and 31 through 33. Each driving circuit 40receives the output signal SA1, SA2, SA3, SB1, SB2 or SB3 of thecontroller 15 as a driving signal for driving the correspondingswitching transistor 21, 22, 23, 31, 32 or 33. The voltage at the drainterminal of each of the switching transistors 21 through 23 and 31through 33 is smoothed by the smoothing circuit 10 to be output as theoutput voltage Vout.

[0052] The respective output switching transistors 21 through 23 havedifferent transistor widths, which become larger in the order of theswitching transistors 21, 22 and 23 (21<22<23). As a result, theon-resistances thereof are larger in the order of the switchingtransistors 23, 22 and 21 (23<22<21). Similarly, the respectiverectifier switching transistors 31 through 33 have different transistorwidths, which become larger in the order of the rectifier switchingtransistors 31, 32 and 33 (31<32<33). As a result, the on-resistancesthereof are larger in the order of the rectifier switching transistors33, 32 and 31 (33<32<31).

[0053] In this embodiment, the plural output switching transistors 21through 23 and the plural rectifier switching transistors 31 through 33are operated in a predetermined order in their on and off operations.Thus, a current can be prevented from abruptly changing in the switchingoperation, so as to reduce switching noise.

[0054]FIG. 2 is a diagram for showing the internal configuration of thepulse generating circuit 16, and FIG. 3 is a diagram for showing changewith time of the output signal SG of the voltage comparator 4 and theoutput signals SA1 through SA3 and SB1 through SB3 of the pulsegenerating circuit 16.

[0055] As is shown in FIG. 3, at a fall of the signal SG, the respectivesignals SA1 through SA3 and SB1 through SB3 successively fall in apredetermined order. When it is herein assumed that the logic of thesignal is not inverted in each driving circuit 40, the output switchingtransistors 21 through 23, that is, the P-type MOS transistors, conductthe on operation in response to the falls of the signals SA1 throughSA3, and the rectifier switching transistors 31 through 33, that is, theN-type MOS transistors, conduct the off operation in response to thefalls of the signals SB1 through SB3. On the other hand, at a rise ofthe signal SG, the respective signals SA1 through SA3 and SB1 throughSB3 successively rise in a predetermined order. As a result, the outputswitching transistors 21 through 23 conduct the off operation and therectifier switching transistors 31 through 33 conduct the on operation.

[0056] In the on operation, the output switching transistors 21 through23 are operated in accordance with the signals SA1 through SA3 in theascending order of transistor width, namely, in the descending order ofon-resistance. Specifically, the output switching transistor 21 havingthe smallest transistor width is turned on first, the output switchingtransistor 22 is turned on next, and the output switching transistor 23having the largest transistor width is turned on lastly. On the otherhand, in the off operation, the output switching transistors 21 through23 are operated in the descending order of transistor width, namely, inthe ascending order of on-resistance. Specifically, the output switchingtransistor 23 having the largest transistor width is turned on first,the output switching transistor 22 is turned on next, and the outputswitching transistor 21 having the smallest transistor width is turnedon lastly.

[0057] Similarly, in the on operation, the rectifier switchingtransistors 31 through 33 are operated in accordance with the signalsSB1 through SB3 in the ascending order of transistor width, namely, inthe descending order of on-resistance (31→32→33). On the other hand, inthe off operation, the rectifier switching transistors 31 through 33 areoperated in the descending order of transistor width, namely, in theascending order of on-resistance (33→32→31).

[0058] Such switching operations can suppress the abrupt change of thedrain current, resulting in reducing the L·di/dt noise derived from aparasitic inductor 102.

[0059] Next, determination of the transistor widths of the pluralswitching transistors 20 of this embodiment will be described. FIG. 4 isa diagram for showing the characteristics of the output switchingtransistors 21 through 23. In FIG. 4, it is assumed for the sake ofunderstanding that the gate potentials of the respective outputswitching transistors 21 through 23 are set to fall at the same time.

[0060] First, the total size, namely, the total transistor width, of theplural output switching transistors is determined. In order to attainhigh conversion efficiency in a switching regulator, it is preferredthat the on-resistance of each output switching transistor is as smallas possible. In order to reduce the on-resistance, it is necessary toincrease the transistor width, and hence, there is a trade-offrelationship between the high efficiency and the area of the transistor.Also, when the transistor width is large, the parasitic capacitance ofthe transistor is increased, which elongates response time of thetransistor serving as a switching device. Therefore, large switchingloss and charge/discharge loss are caused by the switching device itselfduring the on/off operation.

[0061] Accordingly, the size determination of an output switchingtransistor is a significant factor in the design of a highly efficientswitching regulator, and it is necessary to select an optimal size inconsideration of the above-described matters. After the total size ofthe output switching transistors is determined, the transistor width ofeach switching transistor is determined.

[0062] First, the transistor width of the output switching transistor 21at the first stage is determined so that a drain current value in anon-saturation region of the drain voltage-current characteristic can belarger than the maximum load current value to be output by the switchingregulator. In FIG. 4, a point A corresponds to a boundary between anon-saturation region and a saturation region in the characteristic ofthe output switching transistor 21, and a current value at the point Ais larger than the maximum load current value Imax of the switchingregulator. Herein, the transistor width of the output switchingtransistor 21 is determined as, for example, 1 mm.

[0063] In the case where the output switching transistor 21 at the firststage alone is in an on state, if the load current value of theswitching regulator is larger than the drain current of the outputswitching transistor 21 at the first stage, the supply current from thediode 11 is large. When the output switching transistor 22 at the nextstage is turned on under this condition, abrupt current change iscaused, which causes the noise. In order to prevent this noise, it ispreferred that the output switching transistor 21 at the first stage isconstructed to have a drain current in the non-saturation region of itscharacteristic larger than the maximum load current value of theswitching regulator.

[0064] Next, with respect to the output switching transistor 22 at thenext stage, a switching interval is set so that the output switchingtransistor 22 can be turned on when the characteristic of the outputswitching transistor 21 reaches the non-saturation region from thesaturation region. Then, the transistor width of the output switchingtransistor 22 is determined so that a time change ratio of a draincurrent, di/dt, can be constant at a drain-source voltage VDS attainedwhen the characteristic of the output switching transistor 21 at thefirst stage reaches the non-saturation region from the saturationregion. Herein, the transistor width of the output switching transistor22 is determined as, for example, 3 mm.

[0065] Furthermore, with respect to the output switching transistor 23at the subsequent stage, the transistor width is determined so that thetime change ratio of a drain current, di/dt, can be constant when it isturned on. Herein, the transistor width of the output switchingtransistor 23 is determined as, for example, 10 mm.

[0066] Also with respect to the rectifier switching transistors 31through 33, the transistor widths can be determined in the same manneras described above.

[0067] In this manner, according to this embodiment, the plural outputswitching transistors are successively turned on in the descending orderof on-resistance and turned off in the ascending order of on-resistance,and the transistor widths of the output switching transistors areoptimized so as to make substantially constant the time change ratio ofthe current, di/dt. Accordingly, the abrupt current change can beprevented in the switching operation of the output switchingtransistors, resulting in reducing the noise derived from the parasiticinductor.

[0068] Although both the output switching transistors and the rectifierswitching transistors are provided at plural stages in this embodiment,the rectifier switching transistors are not necessarily provided at theplural stages. The effect to reduce the switching noise can be achievedeven when the output switching transistors alone are provided at theplural stages. However, by providing plural rectifier switchingtransistors, the noise can be reduced more effectively.

[0069] Also, the output switching transistors or the rectifier switchingtransistors can be operated in the predetermined order merely in eitherthe on operation or the off operation.

[0070] Alternatively, the on-resistances of the output switchingtransistors and the rectifier switching transistors can be differentlyset by using a factor other than the transistor width.

[0071]FIG. 5 shows another exemplified configuration of the pluraloutput switching transistors. The plural output switching transistors20A of FIG. 5 includes eight transistors with an equal transistor widthdivided into three groups. Specifically, a first group 24 consists of atransistor 24 a, a second group 25 consists of transistors 25 a through25 c, and a third group 26 consists of transistors 26 a through 26 e.

[0072] In this case, the controller 15 turns on or off the plural outputswitching transistors 20A by group. Specifically, the transistor 24 a ofthe first group 24 is controlled in accordance with the signal SA1, thetransistors 25 a through 25 c of the second group 25 are controlled inaccordance with the signal SA2, and the transistors 26 a through 26 e ofthe third group 26 are controlled in accordance with the signal SA3.

[0073] The number of transistors belonging to each group is determinedas follows: FIG. 6 is a diagram for showing the characteristics of thetransistors belonging to the groups 24 through 26. Also in FIG. 6, it isassumed for the sake of understanding that the gate potentials of therespective output switching transistors are set to fall at the sametime.

[0074] First, the number of transistors belonging to the first group 24is determined so that a drain current value in a non-saturation regionof the drain voltage-current characteristic can be larger than themaximum load current value to be output by the switching regulator. InFIG. 6, a point A corresponds to a boundary between a non-saturationregion and a saturation region in the characteristic of the transistorbelonging to the first group 24, and a current value at the point A islarger than the maximum load current value Imax of the switchingregulator.

[0075] Next, with respect to transistors belonging to the second group25, a switching interval is set so that they can be turned on when thecharacteristic of the transistor belonging to the first group 24 reachesthe non-saturation region from the saturation region. Then, the numberof transistors belonging to the second group 25 is determined as amaximum number so that a time change ratio di/dt of the total draincurrent can be constant at the drain-source voltage VDS attained whenthe characteristic of the transistor belonging to the first group 24reaches the non-saturation region from the saturation region. Herein,the number of transistors belonging to the second group is determined asthree.

[0076] Furthermore, the number of transistors belonging to the thirdgroup 26 is determined so that the time change ratio di/dt of the totaldrain current can be constant when they are turned on. Herein, thenumber of transistors belonging to the third group is determined asfive.

[0077] In this manner, the number of transistors belonging to each groupis determined so as to make the time change ratio di/dt of the currentconstant, and the transistors are turned on in the on operation so thata larger number of transistors can be successively turned on and areturned off in the off operation so that a smaller number of transistorscan be successively turned off. As a result, the abrupt current changecan be prevented in the switching operation of the output switchingtransistors, so as to reduce the noise derived from the parasiticinductor.

[0078] Although the number of transistors belonging to the first groupto be turned on first is one in the above-described case, pluraltransistors can be turned on first.

[0079] Next, the internal configuration of the driving circuit 40 ofFIG. 1 will be described.

[0080]FIG. 7 is a circuit diagram for showing an internal configurationof the driving circuit 40. The driving circuit 40 of FIG. 7 drives theoutput switching transistor 23, and includes an inverter 41 for drivingthe gate of the output switching transistor 23 in accordance with thesignal SA3 and a constant current source circuit 42 for allowing aconstant current I to flow through the inverter 41. In the descriptionof the operation of the switching regulator described with reference toFIG. 1, the logic of a signal is assumed not to be inverted in eachdriving circuit 40, but the driving circuit 40 includes one inverter 41in the description referring to FIG. 7.

[0081] If the driving circuit 40 is constructed merely from the inverter41 including a P-type MOS transistor 41 a and an N-type MOS transistor41 b, current change is so large during charge/discharge of the gatethat the di/dt noise can be caused. Therefore, the driving circuit 40includes the constant current source circuit 42 for controlling thecurrent I flowing through the inverter 41 to be constant as is shown inFIG. 7. Thus, the abrupt current change can be prevented from beingcaused during the charge/discharge of the gate, resulting in preventingthe occurrence of the noise.

[0082] The constant current source circuit 42 as shown in FIG. 7 is notnecessarily provided in all the driving circuits 40 but can be providedin merely part of the driving circuits 40. The di/dt noise derived fromthe current change caused during the charge/discharge of the gate islarger in a transistor with a large transistor width. Therefore, theeffect of reducing the noise can be most remarkably attained when theconstant current source circuit 42 is provided in the driving circuit 40for driving the output switching transistor 23 with the largesttransistor width. It goes without saying that the effect of reducing thenoise can be exhibited also when the constant current source circuit 42is provided in the other driving circuit 40 for driving any of theoutput switching transistors 21 and 23 and the rectifier switchingtransistors 31 through 33, and that the effect of reducing the noise canbe more remarkably attained in the entire switching regulator when theconstant current source circuit 42 is provided in a larger number ofdriving circuits 40.

[0083]FIG. 8 is a circuit diagram for showing another exemplifiedinternal configuration of the driving circuit 40. A driving circuit 40Aof FIG. 8 includes, in addition to the inverter 41 and the constantcurrent source circuit 42, a load current monitoring circuit 43 and acurrent controlling circuit 44. The current controlling circuit 44includes transistors 44 a and 44 b serially connected to each other andparallel connected to a resistance 42 a included in the constant currentsource circuit 42. The load current monitoring circuit 43 controls theon/off operations of the transistors 44 a and 44 b of the currentcontrolling circuit 44 in accordance with the amplitude of a loadcurrent. Thus, the resistance value of the resistance 42 a issubstantially controlled, so as to control the amplitude of the constantcurrent I flowing through the inverter 41.

[0084] When the load current is small, the noise is comparatively small.Therefore, in the case where the gate charge/discharge of the outputswitching transistor or the rectifier switching transistor is sloweddown by the constant current source circuit 42, the efficiency of theswitching regulator is naturally degraded.

[0085] Accordingly, when the load current is small, the resistance 42 aof the constant current source circuit 42 is partly short-circuited bythe current controlling circuit 44, so as to increase the supply currentI to the inverter 41. In this manner, the gate potential is abruptlychanged in the gate charge/discharge of the output switching transistor23, thereby preventing the efficiency degradation.

[0086] The load current monitoring circuit 43 can be realized in any ofvarious configurations. For example, it can include plural comparatorseach for comparing the output voltage Vout with a predeterminedreference voltage, so as to control the transistors 44 a and 44 b of thecurrent controlling circuit 44 in accordance with the outputs of therespective comparators. Alternatively, it can monitor the drain voltageof the output switching transistor 23. Further alternatively, it candetermine the amplitude of the load current in accordance with theoperation state of equipment including the switching regulator. Forexample, in the case where the switching regulator is included in aportable telephone, it can determine that the load current is largeduring a call and is small in a waiting state.

[0087]FIG. 9 is a circuit diagram for showing still another exemplifiedconfiguration of the driving circuit 40. A driving circuit 40B of FIG. 9includes, in addition to the inverter 41 and the constant current sourcecircuit 42, a non-overlap circuit 45.

[0088] In the configurations of FIGS. 7 and 8, the constant currentsource circuit 42 is provided in order to slow down the current changein the gate charge/discharge of the output switching transistor 23. Whenthe current I flowing through the inverter 41 is made too small,however, a longer time is required for the gate charge/discharge, andhence, the efficiency is degraded although the noise can be reduced. Inorder to slow down the current change in the gate charge/discharge ofthe output switching transistor 23 as well as to suppress the efficiencydegradation, the switching of the inverter 41 can be slowed down.

[0089] In this case, however, there is a fear of a time period when theP-type MOS transistor 41 a and the N-type MOS transistor 41 b of theinverter 41 are both in an on state, which can allow a through-currentto flow through the inverter 41.

[0090] Accordingly, in the configuration of FIG. 9, the non-overlapcircuit 45 is provided for gate control of the inverter elements 41 aand 41 b of the inverter 41, so as to prevent the inverter elements 41 aand 41 b from being both placed in an on state. As a result, theoccurrence of the through-current in the inverter 41 can be avoided.

[0091] Furthermore, in inverters 45 a and 45 b f the non-overlap circuit45, the transistor widths of transistors therein are preferablyasymmetrical. Specifically, the transistor width of the transistor inthe inverter 45 a is set so that the output potential thereof can slowlyfall and abruptly rise, thereby slowly turning on and rapidly turningoff the P-type MOS transistor 41 a. Similarly, the transistor width ofthe transistor in the inverter 45 b is set so that the output potentialthereof can slowly rise and abruptly fall, thereby slowly turning on andrapidly turning off the N-type MOS transistor 41 b.

[0092]FIG. 10 is a schematic diagram for showing an exemplified layoutof the output switching transistors 21 through 23 and the rectifierswitching transistors 31 through 33 of FIG. 1. As is shown in figure 10,the transistors 21 and 3l having comparatively large sizes are disposedcomparatively closer to I/O pads while the transistors 23 and 33 havingcomparatively small sizes are disposed comparatively farther from theI/O pads. Since the transistors 21 and 31 with large sizes are providedfor attaining high conversion efficiency, they should be disposed closerto the I/O pads, so as to reduce line resistances by decreasing thelengths of the lines. On the other hand, since the transistors 23 and 33with small sizes are provided for reducing the noise by using their highon-resistances, increase of line resistances due to longer lines byplacing them farther from the I/O pads is rather preferred.

[0093] Also, each of the transistors 21 and 31 also works as a diode forreleasing charge of a surge, and hence, it is preferred, inconsideration of protection from the surge, that the transistors 21 and31 with large sizes are disposed closer to the peripheral portion of anLSI chip.

[0094] (EMBODIMENT 2)

[0095]FIG. 11 is a diagram for showing the configuration of a switchingregulator of Embodiment 2 of the invention. In FIG. 11, like referencenumerals are used to refer to like elements used in FIG. 1.

[0096] In the configuration of FIG. 11, a pulse generating circuit 16Aof a controller 15A outputs, in response to an output signal SG of avoltage comparator 4, two signals SA and SB for controlling the on/offoperations of switching transistors 21 through 23 and 31 through 33.Furthermore, each of the switching transistors 21 through 23 and 31through 33 is provided with an edge detecting circuit 60 disposed at aprevious stage of a driving circuit 40. Each edge detecting circuit 60receives, at its inputs A and B, the output signal of the pulsegenerating circuit 16A or a gate signal output from the driving circuit40 correspondingly provided to another switching transistor.

[0097]FIG. 12(a) is a diagram for showing the internal configuration ofthe edge detecting circuit 60, and FIG. 12(b) is a timing chart of theinputs A and B and the output OUT of the edge detecting circuit 60 ofFIG. 12(a). As is shown in FIG. 12(b), the output OUT of the edgedetecting circuit 60 becomes high at the rise edge of the input A andbecomes low at the fall edge of the input B.

[0098] Now, the operation of the switching regulator of FIG. 11 will bedescribed.

[0099] The output switching transistors 21 through 23 are operated asfollows: In the on operation of the output switching transistors 21through 23, the signal SA of the pulse generating circuit 16A undergoesa low transition. In response to this fall of the signal SA, the outputswitching transistor 21 having the largest on-resistance is first turnedon. Next, in response to the fall of the gate signal of the outputswitching transistor 21, the output switching transistor 22 at the nextstage is turned on. Similarly, in response to the fall of the gatesignal of the output switching transistor 22, the output switchingtransistor 23 having the smallest on-resistance is turned on.Specifically, the output switching transistors 21 through 23 aresuccessively turned on in the descending order of on-resistance inresponse to the fall of the output signal SA of the pulse generatingcircuit 16A.

[0100] On the other hand, in the off operation of the output switchingtransistors 21 through 23, the signal SA of the pulse generating circuit16A undergoes a high transition. In response to this rise of the signalSA, the output switching transistor 23 having the smallest on-resistanceis turned off first. Next, in response to the rise of the gate signal ofthe output switching transistor 23, the output switching transistor 22is turned off, and similarly, in response to the rise of the gate signalof the output switching transistor 22, the output switching transistor21 is turned off. Specifically, the output switching transistors 21through 23 are successively turned off in the ascending order ofon-resistance in response to the rise of the output signal SA of thepulse generating circuit 16A.

[0101] The rectifier switching transistors 31 through 33 are similarlyoperated. In the on operation of the rectifier switching transistors 31through 33, the signal SB of the pulse generating circuit 16A undergoesa high transition. In response to this rise of the signal SB, therectifier switching transistor 31 having the largest on-resistance isturned on. In response to the rise of the gate signal of the rectifierswitching transistor 31, the rectifier switching transistor 32 is turnedon, and in response to the rise of the gate signal of the rectifierswitching transistor 32, the rectifier switching transistor 33 havingthe smallest on-resistance is turned on. On the other hand, in the offoperation of the rectifier switching transistors 31 through 33, thesignal SB of the pulse generating circuit 16A undergoes a lowtransition. In response to this fall of the signal SB, the rectifierswitching transistor 33 having the smallest on-resistance is turned off,and thereafter, the rectifier switching transistors 32 and 31 aresuccessively turned off. Specifically, the rectifier switchingtransistors 31 through 33 are successively turned on in the descendingorder of on-resistance in response to the rise of the output signal SBof the pulse generating circuit 16A, and are successively turned off inthe ascending order of on-resistance in response to the fall of thesignal SB.

[0102] In this manner, the on/off operations of the output and rectifierswitching transistors are controlled in accordance with the two pulsesignals SA and SB output from the pulse generating circuit 16A in thisembodiment. Accordingly, even when the number of stages of the switchingtransistors is increased, there is no need to increase the numbers ofgate control signals and signal lines.

[0103] (Embodiment 3)

[0104]FIG. 13 is a diagram for showing the configuration of a switchingregulator of Embodiment 3 of the invention. In FIG. 13, like referencenumerals are used to refer to like elements used in FIG. 11.

[0105] In the configuration of FIG. 13, a pulse generating circuit 16Bincluded in a controller 15B outputs one signal SX, which is supplied toan input A of an edge detecting circuit 60 corresponding to an outputswitching transistor 23 having the smallest on-resistance, to an input Bof an edge detecting circuit 60 corresponding to a rectifier switchingtransistor 33 having the smallest on-resistance and to one input of anOR gate 65. To the other input of the OR gate 65, agate signal of arectifier switching transistor 31 having the largest on-resistance issupplied. The output of the OR gate 65 is supplied to an input B of anedge detecting circuit 60 corresponding to an output switchingtransistor 21 having the largest on-resistance. Also, to an input A ofan edge detecting circuit 60 corresponding to the rectifier switchingtransistor 31 having the largest on-resistance, a gate signal of theoutput switching transistor 21 is supplied. The configuration of FIG. 13is the same as that of FIG. 11 except for the above.

[0106] In the on operation of the output switching transistors 21through 23 and the off operation of the rectifier switching transistor31 through 33, the signal SX of the pulse generating circuit 16Bundergoes a low transition. As a result, the rectifier switchingtransistor 33 is first turned off, and the rectifier switchingtransistors 32 and 3l are successively turned off. Then, the output ofthe OR gate 65 falls in response to a fall of the gate signal of therectifier switching transistor 31, so as to turn on the output switchingtransistor 21. Thereafter, the output switching transistors 22 and 23are successively turned on.

[0107] On the other hand, in the off operation of the output switchingtransistors 21 through 23 and the on operation of the rectifierswitching transistors 31 through 33, the signal SX of the pulsegenerating circuit 16B undergoes a high transition. As a result, theoutput switching transistor 23 is turned off, and then, the outputswitching transistors 22 and 21 are successively turned off. Then, therectifier switching transistor 31 is turned on in response to a rise ofthe gate signal of the output switching transistor 21. Thereafter, therectifier switching transistors 32 and 33 are successively turned on.

[0108] In this manner, the on operation and the off operation of theoutput switching transistors 21 through 23 are respectively carried outcontinuously to the off operation and the on operation of the rectifierswitching transistors 31 through 33 in this embodiment. Also, the on/offoperations of the output and rectifier switching transistors can becontrolled in accordance with one pulse signal SX output from the pulsegenerating circuit 16B. Accordingly, even when the number of stages ofthe switching transistors is increased, there is no need to increase thenumbers of gate control signals and signal lines.

[0109] (EMBODIMENT 4)

[0110]FIG. 14 is a diagram for showing part of the configuration of aswitching regulator of Embodiment 4 of the invention. FIG. 14 shows theconfiguration related to an output switching transistor 21 alone, inwhich a reference numeral 71 denotes a load current monitoring circuit,reference numerals 72 a and 72 b denote delay circuits each including aninverter chain, and reference numerals 73 a and 73 b denote selectioncircuits each for outputting an input A as an output OUT when aselection input S is at a low level and outputting an input B as theoutput OUT when the selection input S is at a high level. The delaycircuits 72 a and 72 b and the selection circuits 73 a and 73 b togetherform a timing setting circuit.

[0111] The load current monitoring circuit 71 monitors a load currentquantity of the switching regulator, so as to output a signal at a lowlevel when the load current quantity is small and a signal at a highlevel when the load current quantity is large. As a result, a delaybetween change of the gate signal of an output switching transistor 22or change of the signal SA and change of the gate signal of the outputswitching transistor 21 is small when the load current is small, and islarger correspondingly to a delay obtained by the delay circuits 72 aand 72 b when the load current is large. Accordingly, when the loadcurrent is small, a sequential switching interval can be reduced, sothat the degradation of the efficiency can be more effectivelysuppressed when the load current is small.

[0112] The configuration of FIG. 14 can be provided also to the otheroutput switching transistors or rectifier switching transistors.Furthermore, two kinds of delays can be set in accordance with theamplitude of the load current in the configuration of FIG. 14, but theconfiguration can be modified so that more than two kinds of delays canbe set. FIG. 15 shows an exemplified circuit having a configuration inwhich four kinds of delays can be set.

[0113] In this manner, each sequential switching interval can beappropriately set in this embodiment, and hence, the degradation of theefficiency can be suppressed when the load current is small.

[0114] (EMBODIMENT 5)

[0115]FIG. 16 is a circuit diagram for showing the configuration of aswitching regulator of Embodiment 5 of the invention. In any of theaforementioned embodiments, when an output switching transistor and arectifier switching transistor are both in an on state, athrough-current flows therethrough. In the configuration of FIG. 16, alogic circuit 80 is provided for avoiding the occurrence of thethrough-current.

[0116] In the logic circuit 80 of FIG. 16, a 3-input AND circuit 81receives, as its inputs, driving signals SA1 through SA3 forrespectively driving output switching transistors 21 through 23. A2-input AND circuits 82 a through 82 c receive, as one of their inputs,driving signals SB1 through SB3 for respectively driving rectifierswitching transistors 31 through 33, and also receive, as the otherinputs, the output of the 3-input AND circuit 81.

[0117] Owing to this configuration, when any of the plural outputswitching transistors 21 through 23 is in an on state, the output of the3-input AND circuit 81 is at a low level. Therefore, the pluralrectifier switching transistors 31 through 33 are all placed in an offstate regardless of the logic levels of the control signals SB1 throughSB3. Accordingly, the occurrence of the through-current can be avoided.

[0118] In this embodiment, since the number of output switchingtransistors is three, the 3-input AND circuit is used. Needless to say,the number of inputs of the AND circuit can be changed in accordancewith the number of output switching transistors. Also, the logic circuitcan be in any configuration as far as it can control the switchingtransistors so that when any of the plural output switching transistorsis in an on state, the plural rectifier switching transistors are allplaced in an off sate.

[0119] Now, fabrication of a switching regulator as an LSI will becomplementarily described. As described above, in order to realize aswitching regulator with high conversion efficiency, it is significantto reduce the on-resistances of switching transistors as much aspossible. Also, the loss due to resistance components of lines andbonding wires cannot be ignored when a load current is large.Furthermore, when the switching regulator is used in portable equipment,outside components should be as few as possible and as small as possibleso that the portable equipment can be in smaller shape and weight.

[0120] In consideration of the aforementioned points, a switchingtransistor is preferably fabricated as an on-chip with its on-resistancereduced as far as possible. Alternatively, a switching transistor with asmall on-resistance alone can be fabricated outside with othertransistors constructed as anon-chip. Thus, the switching noise can bereduced with keeping high conversion efficiency and with reducing thenumber of outside components.

[0121]FIG. 17 is a diagram for showing an example of an LSI systemconstructed by using the switching regulator of this invention. In FIG.17, an LSI 90 includes an LSI core part 91 and a DC/DC converter 92, andis provided with a smoothing circuit 10 as an outside component.Reference numerals 93 a through 93 e denote pads of the LSI 90. TheDC/DC converter 92 includes, for example, plural output switchingtransistors as described in any of the aforementioned embodiments, andthe DC/DC converter 92 and the smoothing circuit 10 together form theswitching regulator of this invention. The DC/DC converter 92 convertspower-supply potentials Vdd and Vss supplied at the pads 93 a and 93 binto a voltage Vnd through the operation described in any of theaforementioned embodiments, and outputs the voltage to the pad 93 c. Thesmoothing circuit 10 smoothes the output voltage Vnd of the DC/DCconverter 92 so as to output the smoothed voltage as a voltage Vout. Theoutput voltage Vout of the smoothing circuit 10 is supplied as aninternal power-supply voltage to the LSI core part 91.

1. A switching regulator comprising: plural output switching transistorsoperated in a predetermined order in at least one of an on operation andan off operation thereof.
 2. The switching regulator of claim 1, whereinsaid plural output switching transistors are turned on in a descendingorder of on-resistance in the on operation thereof, and said pluraloutput switching transistors are turned off in an ascending order ofon-resistance in the off operation thereof.
 3. The switching regulatorof claim 1, wherein said plural output switching transistors are turnedon in an ascending order of transistor width in the on operationthereof, and said plural output switching transistors are turned off ina descending order of transistor width in the off operation thereof. 4.The switching regulator of claim 1, wherein one of said plural outputswitching transistors that is turned on first has a drain current valuein a non-saturation region larger than a maximum load current value ofsaid switching regulator.
 5. The switching regulator of claim 1, whereinsaid plural output switching transistors are divided into plural groups,and in the on operation thereof, said plural output switchingtransistors are turned on by group in an ascending order of the numberof output switching transistors belonging to each group, and in the offoperation thereof, said plural output switching transistors are turnedoff by group in a descending order of the number of output switchingtransistors belonging to each group.
 6. The switching regulator of claim1, further comprising plural driving circuits provided correspondinglyto said plural output switching transistors each for operating acorresponding one of said output switching transistors in accordancewith a driving signal thereof, wherein at least one of said pluraldriving circuits includes: an inverter for driving a gate of thecorresponding one of said output switching transistors in accordancewith said driving signal; and a constant current source circuit forcontrolling a current flowing through said inverter to be constant. 7.The switching regulator of claim 6, wherein said at least one of saidplural driving circuits includes a current controlling circuit forcontrolling, in accordance with a load current quantity of saidswitching regulator, an amplitude of the current flowing through saidinverter controlled by said constant current source circuit.
 8. Theswitching regulator of claim 6, wherein said at least one of said pluraldriving circuits includes a non-overlap circuit that receives saiddriving signal and supplies a signal to said inverter for preventing aP-type MOS transistor and an N-type MOS transistor included in saidinverter from being in an on state at the same time.
 9. The switchingregulator of claim 1, wherein one of said plural output switchingtransistors having a comparatively large size is placed comparativelycloser to I/O pads of an LSI including said switching regulator andanother of said plural output switching transistors having acomparatively small size is placed comparatively farther from the I/Opads of said LSI.
 10. The switching regulator of claim 1, furthercomprising a timing setting circuit provided correspondingly to at leastone of said plural output switching transistors, said timing settingcircuit setting timing of the corresponding one of said output switchingtransistors to be turned on or off in accordance with a load currentvalue of said switching regulator.
 11. The switching regulator of claim1, further comprising plural rectifier switching transistors operated ina predetermined order in at least one of an on operation and an offoperation thereof.
 12. The switching regulator of claim 11, wherein saidplural rectifier switching transistors are turned on in a descendingorder of on-resistance in the on operation thereof, and said pluralrectifier switching transistors are turned off in an ascending order ofon-resistance in the off operation thereof.
 13. The switching regulatorof claim 11, further comprising plural driving circuits providedcorrespondingly to said plural rectifier switching transistors each foroperating a corresponding one of said plural rectifier switchingtransistors in accordance with a driving signal thereof, wherein atleast one of said plural driving circuits includes: an inverter fordriving a gate of the corresponding one of said rectifier switchingtransistors in accordance with said driving signal; and a constantcurrent source circuit for controlling a current flowing through saidinverter to be constant.
 14. The switching regulator of claim 11,further comprising a timing setting circuit provided correspondingly toat least one of said plural rectifier switching transistors for settingtiming of the corresponding one of said output switching transistors tobe turned on or off in accordance with a load current value of saidswitching regulator.
 15. The switching regulator of claim 11, furthercomprising a logic circuit for preventing said plural rectifierswitching transistors from turning on when at least one of said pluraloutput switching transistors is in an on state.
 16. The switchingregulator of claim 1, further comprising a controller for controllingthe on operation and the off operation of said plural output switchingtransistors, wherein, in the on operation of said plural outputswitching transistors, said controller turns on one of said outputswitching transistors that is to be turned on first, and the rest ofsaid output switching transistors are successively turned on inaccordance with change of a gate signal of any of said output switchingtransistors that is turned on immediately before, and in the offoperation of said plural output switching transistors, said controllerturns off one of said output switching transistors that is to be turnedoff first, and the rest of said output switching transistors aresuccessively turned off in accordance with change of a gate signal ofany of said output switching transistors that is turned off immediatelybefore.
 17. The switching regulator of claim 16, further comprisingplural rectifier switching transistors operated in a predetermined orderin an on operation and an off operation thereof, wherein, in the onoperation of said plural output switching transistors, said controllerturns off one of said rectifier switching transistors that is to beturned off first, and the rest of said rectifier switching transistorsare successively turned off in accordance with change of a gate signalof any of said rectifier switching transistors that is turned offimmediately before, and one of said output switching transistors that isto be turned on first is turned on in accordance with change of a gatesignal of any of said rectifier switching transistors that is turned offlastly, and the rest of said output switching transistors aresuccessively turned on in accordance with change of a gate signal of anyof said output switching transistors that is turned on immediatelybefore, and in the off operation of said plural output switchingtransistors, said controller turns off one of said output switchingtransistors that is to be turned off first, and the rest of said outputswitching transistors are successively turned off in accordance withchange of a gate signal of any of said output switching transistors thatis turned off immediately before, and one of said rectifier switchingtransistors that is to be turned on first is turned on in accordancewith change of a gate signal of any of said output switching transistorsthat is turned off lastly, and the rest of said rectifier switchingtransistors are successively turned on in accordance with change of agate signal of any of said rectifier switching transistors that isturned on immediately before.
 18. An LSI system comprising: saidswitching regulator of claim 1; and an LSI core part operated by avoltage supplied from said switching regulator.